Messages in this thread Patch in this message | | | From | Greg Kroah-Hartman <> | Subject | [PATCH 5.19 0669/1157] iio: addac: ad74413r: Fix alignment for DMA safety | Date | Mon, 15 Aug 2022 20:00:25 +0200 |
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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[ Upstream commit 00eb2b8a077062557772234019ecd6045b8b6298 ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: fea251b6a5db ("iio: addac: add AD74413R driver") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Cosmin Tanislav <cosmin.tanislav@analog.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-41-jic23@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/iio/addac/ad74413r.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/addac/ad74413r.c b/drivers/iio/addac/ad74413r.c index acd230a6af35..6a66d7a65db7 100644 --- a/drivers/iio/addac/ad74413r.c +++ b/drivers/iio/addac/ad74413r.c @@ -77,13 +77,13 @@ struct ad74413r_state { struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ struct { u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; s64 timestamp; - } adc_samples_buf ____cacheline_aligned; + } adc_samples_buf __aligned(IIO_DMA_MINALIGN); u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; u8 reg_tx_buf[AD74413R_FRAME_SIZE]; -- 2.35.1
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