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    Subject[PATCH 5.19 0634/1157] iio: accel: adxl367: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit e1f956a804df9074fb5de557563d153ae25252e7 ]

    ____cacheline_aligned is insufficient guarantee for non-coherent DMA.
    Switch to the updated IIO_DMA_MINALIGN definition.

    Update comment to reflect that DMA safety may require separate
    cachelines.

    Fixes: cbab791c5e2a5 ("iio: accel: add ADXL367 driver")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Cc: Cosmin Tanislav <demonsingur@gmail.com>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-5-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/accel/adxl367.c | 2 +-
    drivers/iio/accel/adxl367_spi.c | 8 +++++---
    2 files changed, 6 insertions(+), 4 deletions(-)

    diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c
    index 0289ed8cf2c6..0168329ec505 100644
    --- a/drivers/iio/accel/adxl367.c
    +++ b/drivers/iio/accel/adxl367.c
    @@ -179,7 +179,7 @@ struct adxl367_state {
    unsigned int fifo_set_size;
    unsigned int fifo_watermark;

    - __be16 fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned;
    + __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
    __be16 sample_buf;
    u8 act_threshold_buf[2];
    u8 inact_time_buf[2];
    diff --git a/drivers/iio/accel/adxl367_spi.c b/drivers/iio/accel/adxl367_spi.c
    index 26dfc821ebbe..118c894015a5 100644
    --- a/drivers/iio/accel/adxl367_spi.c
    +++ b/drivers/iio/accel/adxl367_spi.c
    @@ -9,6 +9,8 @@
    #include <linux/regmap.h>
    #include <linux/spi/spi.h>

    +#include <linux/iio/iio.h>
    +
    #include "adxl367.h"

    #define ADXL367_SPI_WRITE_COMMAND 0x0A
    @@ -28,10 +30,10 @@ struct adxl367_spi_state {
    struct spi_transfer fifo_xfer[2];

    /*
    - * DMA (thus cache coherency maintenance) requires the
    - * transfer buffers to live in their own cache lines.
    + * DMA (thus cache coherency maintenance) may require the
    + * transfer buffers live in their own cache lines.
    */
    - u8 reg_write_tx_buf[1] ____cacheline_aligned;
    + u8 reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN);
    u8 reg_read_tx_buf[2];
    u8 fifo_tx_buf[1];
    };
    --
    2.35.1


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