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    Subject[PATCH 5.19 0068/1157] riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit
    Date
    From: Chen Lifu <chenlifu@huawei.com>

    commit c08b4848f596fd95543197463b5162bd7bab2442 upstream.

    Since commit 5d8544e2d007 ("RISC-V: Generic library routines and assembly")
    and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code"),
    if __clear_user and __copy_user return from an fixup branch,
    CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that
    S-mode memory accesses to pages that are accessible by U-mode will success.
    Disable S-mode access to U-mode memory should clear SR_SUM bit.

    Fixes: 5d8544e2d007 ("RISC-V: Generic library routines and assembly")
    Fixes: ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code")
    Signed-off-by: Chen Lifu <chenlifu@huawei.com>
    Reviewed-by: Ben Dooks <ben.dooks@codethink.co.uk>
    Link: https://lore.kernel.org/r/20220615014714.1650349-1-chenlifu@huawei.com
    Cc: stable@vger.kernel.org
    Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/riscv/lib/uaccess.S | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    --- a/arch/riscv/lib/uaccess.S
    +++ b/arch/riscv/lib/uaccess.S
    @@ -175,7 +175,7 @@ ENTRY(__asm_copy_from_user)
    /* Exception fixup code */
    10:
    /* Disable access to user memory */
    - csrs CSR_STATUS, t6
    + csrc CSR_STATUS, t6
    mv a0, t5
    ret
    ENDPROC(__asm_copy_to_user)
    @@ -227,7 +227,7 @@ ENTRY(__clear_user)
    /* Exception fixup code */
    11:
    /* Disable access to user memory */
    - csrs CSR_STATUS, t6
    + csrc CSR_STATUS, t6
    mv a0, a1
    ret
    ENDPROC(__clear_user)

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