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    Subject[PATCH 5.18 0623/1095] iio: adc: ti-tlc4541: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit 62fa19bf484bfeb52c56b7c6d6a6b1222c597f9c ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Update the comment to include 'may'.

    Fixes: ac2bec9d587c ("iio: adc: tlc4541: add support for TI tlc4541 adc")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-40-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/adc/ti-tlc4541.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/iio/adc/ti-tlc4541.c b/drivers/iio/adc/ti-tlc4541.c
    index 2406eda9dfc6..30f629a553a1 100644
    --- a/drivers/iio/adc/ti-tlc4541.c
    +++ b/drivers/iio/adc/ti-tlc4541.c
    @@ -37,12 +37,12 @@ struct tlc4541_state {
    struct spi_message scan_single_msg;

    /*
    - * DMA (thus cache coherency maintenance) requires the
    + * DMA (thus cache coherency maintenance) may require the
    * transfer buffers to live in their own cache lines.
    * 2 bytes data + 6 bytes padding + 8 bytes timestamp when
    * call iio_push_to_buffers_with_timestamp.
    */
    - __be16 rx_buf[8] ____cacheline_aligned;
    + __be16 rx_buf[8] __aligned(IIO_DMA_MINALIGN);
    };

    struct tlc4541_chip_info {
    --
    2.35.1


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