Messages in this thread Patch in this message | | | From | Greg Kroah-Hartman <> | Subject | [PATCH 5.18 0618/1095] iio: adc: ti-ads124s08: Fix alignment for DMA safety | Date | Mon, 15 Aug 2022 20:00:17 +0200 |
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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[ Upstream commit 7df19bd26cc0b85ff997cc9e2aaea712836b5460 ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Fixes: e717f8c6dfec ("iio: adc: Add the TI ads124s08 ADC code") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-35-jic23@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/iio/adc/ti-ads124s08.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/adc/ti-ads124s08.c b/drivers/iio/adc/ti-ads124s08.c index 767b3b634809..64833156c199 100644 --- a/drivers/iio/adc/ti-ads124s08.c +++ b/drivers/iio/adc/ti-ads124s08.c @@ -106,7 +106,7 @@ struct ads124s_private { * timestamp is maintained. */ u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u32)] __aligned(8); - u8 data[5] ____cacheline_aligned; + u8 data[5] __aligned(IIO_DMA_MINALIGN); }; #define ADS124S08_CHAN(index) \ -- 2.35.1
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