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    Subject[PATCH 5.18 0621/1095] iio: adc: ti-ads8344: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit 8966b11e5a14aaabc747ee97a7942fd50a681402 ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Fixes: 8dd2d7c0fed7 ("iio: adc: Add driver for the TI ADS8344 A/DC chips")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-38-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/adc/ti-ads8344.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/iio/adc/ti-ads8344.c b/drivers/iio/adc/ti-ads8344.c
    index c96d2a9ba924..bbd85cb47f81 100644
    --- a/drivers/iio/adc/ti-ads8344.c
    +++ b/drivers/iio/adc/ti-ads8344.c
    @@ -28,7 +28,7 @@ struct ads8344 {
    */
    struct mutex lock;

    - u8 tx_buf ____cacheline_aligned;
    + u8 tx_buf __aligned(IIO_DMA_MINALIGN);
    u8 rx_buf[3];
    };

    --
    2.35.1


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