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    Subject[PATCH 5.18 0545/1095] clk: renesas: rzg2l: Fix reset status function
    Date
    From: Biju Das <biju.das.jz@bp.renesas.com>

    [ Upstream commit 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 ]

    As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means
    reset signal is not applied (deassert state) and 1 means reset signal
    is applied (assert state).

    reset_control_status() expects a positive value if the reset line is
    asserted. But rzg2l_cpg_status function returns zero for asserted
    state.

    This patch fixes the issue by adding double inverted logic, so that
    reset_control_status returns a positive value if the reset line is
    asserted.

    Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
    Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
    Link: https://lore.kernel.org/r/20220531071657.104121-1-biju.das.jz@bp.renesas.com
    Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/renesas/rzg2l-cpg.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
    index 486d0656c58a..1068058a3865 100644
    --- a/drivers/clk/renesas/rzg2l-cpg.c
    +++ b/drivers/clk/renesas/rzg2l-cpg.c
    @@ -744,7 +744,7 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
    unsigned int reg = info->resets[id].off;
    u32 bitmask = BIT(info->resets[id].bit);

    - return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
    + return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
    }

    static const struct reset_control_ops rzg2l_cpg_reset_ops = {
    --
    2.35.1


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