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    Subject[PATCH 5.18 0069/1095] RISC-V: Fix counter restart during overflow for RV32
    Date
    From: Atish Patra <atishp@rivosinc.com>

    commit acc1b919f47926b089be21b8aaa29ec91fef0aa2 upstream.

    Pass the upper half of the initial value of the counter correctly
    for RV32.

    Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
    Signed-off-by: Atish Patra <atishp@rivosinc.com>
    Reviewed-by: Guo Ren <guoren@kernel.org>
    Cc: stable@vger.kernel.org
    Link: https://lore.kernel.org/r/20220711174632.4186047-2-atishp@rivosinc.com
    Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/perf/riscv_pmu_sbi.c | 5 +++++
    1 file changed, 5 insertions(+)

    diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
    index dca3537a8dcc..0cb694b794ae 100644
    --- a/drivers/perf/riscv_pmu_sbi.c
    +++ b/drivers/perf/riscv_pmu_sbi.c
    @@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
    hwc = &event->hw;
    max_period = riscv_pmu_ctr_get_width_mask(event);
    init_val = local64_read(&hwc->prev_count) & max_period;
    +#if defined(CONFIG_32BIT)
    + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
    + flag, init_val, init_val >> 32, 0);
    +#else
    sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
    flag, init_val, 0, 0);
    +#endif
    }
    ctr_ovf_mask = ctr_ovf_mask >> 1;
    idx++;
    --
    2.37.1


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