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    Subject[PATCH 5.18 0063/1095] riscv: dts: starfive: correct number of external interrupts
    Date
    From: Mark Kettenis <kettenis@openbsd.org>

    commit a208acf0eac857dc8cdaddd63a4e18ed03f91786 upstream.

    The PLIC integrated on the Vic_U7_Core integrated on the StarFive
    JH7100 SoC actually supports 133 external interrupts. 127 of these
    are exposed to the outside world; the remainder are used by other
    devices that are part of the core-complex such as the L2 cache
    controller. But all 133 interrupts are external interrupts as far
    as the PLIC is concerned. Fix the property so that the driver can
    manage these additional interrupts, which is important since the
    interrupts for the L2 cache controller are enabled by default.

    Fixes: ec85362fb121 ("RISC-V: Add initial StarFive JH7100 device tree")
    Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
    Cc: stable@vger.kernel.org
    Link: https://lore.kernel.org/r/20220707185529.19509-1-kettenis@openbsd.org
    Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
    +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
    @@ -118,7 +118,7 @@
    interrupt-controller;
    #address-cells = <0>;
    #interrupt-cells = <1>;
    - riscv,ndev = <127>;
    + riscv,ndev = <133>;
    };

    clkgen: clock-controller@11800000 {

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