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    Subject[PATCH 5.15 119/779] irqchip/mips-gic: Only register IPI domain when SMP is enabled
    Date
    From: Samuel Holland <samuel@sholland.org>

    [ Upstream commit 8190cc572981f2f13b6ffc26c7cfa7899e5d3ccc ]

    The MIPS GIC irqchip driver may be selected in a uniprocessor
    configuration, but it unconditionally registers an IPI domain.

    Limit the part of the driver dealing with IPIs to only be compiled when
    GENERIC_IRQ_IPI is enabled, which corresponds to an SMP configuration.

    Reported-by: kernel test robot <lkp@intel.com>
    Signed-off-by: Samuel Holland <samuel@sholland.org>
    Signed-off-by: Marc Zyngier <maz@kernel.org>
    Link: https://lore.kernel.org/r/20220701200056.46555-2-samuel@sholland.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/irqchip/Kconfig | 3 +-
    drivers/irqchip/irq-mips-gic.c | 80 +++++++++++++++++++++++-----------
    2 files changed, 56 insertions(+), 27 deletions(-)

    diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
    index aca7b595c4c7..8f9c52873338 100644
    --- a/drivers/irqchip/Kconfig
    +++ b/drivers/irqchip/Kconfig
    @@ -304,7 +304,8 @@ config KEYSTONE_IRQ

    config MIPS_GIC
    bool
    - select GENERIC_IRQ_IPI
    + select GENERIC_IRQ_IPI if SMP
    + select IRQ_DOMAIN_HIERARCHY
    select MIPS_CM

    config INGENIC_IRQ
    diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
    index 54c7092cc61d..f03f47ffea1e 100644
    --- a/drivers/irqchip/irq-mips-gic.c
    +++ b/drivers/irqchip/irq-mips-gic.c
    @@ -51,13 +51,15 @@ static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);

    static DEFINE_SPINLOCK(gic_lock);
    static struct irq_domain *gic_irq_domain;
    -static struct irq_domain *gic_ipi_domain;
    static int gic_shared_intrs;
    static unsigned int gic_cpu_pin;
    static unsigned int timer_cpu_pin;
    static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
    +
    +#ifdef CONFIG_GENERIC_IRQ_IPI
    static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
    static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
    +#endif /* CONFIG_GENERIC_IRQ_IPI */

    static struct gic_all_vpes_chip_data {
    u32 map;
    @@ -460,9 +462,11 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
    u32 map;

    if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
    +#ifdef CONFIG_GENERIC_IRQ_IPI
    /* verify that shared irqs don't conflict with an IPI irq */
    if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
    return -EBUSY;
    +#endif /* CONFIG_GENERIC_IRQ_IPI */

    err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
    &gic_level_irq_controller,
    @@ -551,6 +555,8 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
    .map = gic_irq_domain_map,
    };

    +#ifdef CONFIG_GENERIC_IRQ_IPI
    +
    static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
    const u32 *intspec, unsigned int intsize,
    irq_hw_number_t *out_hwirq,
    @@ -654,6 +660,48 @@ static const struct irq_domain_ops gic_ipi_domain_ops = {
    .match = gic_ipi_domain_match,
    };

    +static int gic_register_ipi_domain(struct device_node *node)
    +{
    + struct irq_domain *gic_ipi_domain;
    + unsigned int v[2], num_ipis;
    +
    + gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
    + IRQ_DOMAIN_FLAG_IPI_PER_CPU,
    + GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
    + node, &gic_ipi_domain_ops, NULL);
    + if (!gic_ipi_domain) {
    + pr_err("Failed to add IPI domain");
    + return -ENXIO;
    + }
    +
    + irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
    +
    + if (node &&
    + !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
    + bitmap_set(ipi_resrv, v[0], v[1]);
    + } else {
    + /*
    + * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
    + * meeting the requirements of arch/mips SMP.
    + */
    + num_ipis = 2 * num_possible_cpus();
    + bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
    + }
    +
    + bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
    +
    + return 0;
    +}
    +
    +#else /* !CONFIG_GENERIC_IRQ_IPI */
    +
    +static inline int gic_register_ipi_domain(struct device_node *node)
    +{
    + return 0;
    +}
    +
    +#endif /* !CONFIG_GENERIC_IRQ_IPI */
    +
    static int gic_cpu_startup(unsigned int cpu)
    {
    /* Enable or disable EIC */
    @@ -672,11 +720,12 @@ static int gic_cpu_startup(unsigned int cpu)
    static int __init gic_of_init(struct device_node *node,
    struct device_node *parent)
    {
    - unsigned int cpu_vec, i, gicconfig, v[2], num_ipis;
    + unsigned int cpu_vec, i, gicconfig;
    unsigned long reserved;
    phys_addr_t gic_base;
    struct resource res;
    size_t gic_len;
    + int ret;

    /* Find the first available CPU vector. */
    i = 0;
    @@ -765,30 +814,9 @@ static int __init gic_of_init(struct device_node *node,
    return -ENXIO;
    }

    - gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
    - IRQ_DOMAIN_FLAG_IPI_PER_CPU,
    - GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
    - node, &gic_ipi_domain_ops, NULL);
    - if (!gic_ipi_domain) {
    - pr_err("Failed to add IPI domain");
    - return -ENXIO;
    - }
    -
    - irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
    -
    - if (node &&
    - !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
    - bitmap_set(ipi_resrv, v[0], v[1]);
    - } else {
    - /*
    - * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
    - * meeting the requirements of arch/mips SMP.
    - */
    - num_ipis = 2 * num_possible_cpus();
    - bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
    - }
    -
    - bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
    + ret = gic_register_ipi_domain(node);
    + if (ret)
    + return ret;

    board_bind_eic_interrupt = &gic_bind_eic_interrupt;

    --
    2.35.1


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