Messages in this thread | | | Date | Thu, 28 Jul 2022 14:03:53 +0300 | Subject | Re: [PATCH 4/8] drm/tidss: Add support for Dual Link LVDS Bus Format | From | Tomi Valkeinen <> |
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On 19/07/2022 11:08, Aradhya Bhatia wrote: > The 2 OLDI TXes in the AM625 SoC can be synced together to output a 2K > resolution video. > > Add support in the driver for the discovery of such a dual mode > connection on the OLDI video port, using the values of "ti,oldi-mode" > property. > > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> > --- > drivers/gpu/drm/tidss/tidss_dispc.c | 39 +++++++++++++++++++++-------- > 1 file changed, 28 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c > index add725fa682b..fb1fdecfc83a 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.c > +++ b/drivers/gpu/drm/tidss/tidss_dispc.c > @@ -853,25 +853,36 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) > } > } > > -enum dispc_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 }; > +enum dispc_oldi_mode_reg_val { > + SPWG_18 = 0, > + JEIDA_24 = 1, > + SPWG_24 = 2, > + DL_SPWG_18 = 4, > + DL_JEIDA_24 = 5, > + DL_SPWG_24 = 6, > +}; > > struct dispc_bus_format { > u32 bus_fmt; > u32 data_width; > bool is_oldi_fmt; > + bool is_dual_link; > enum dispc_oldi_mode_reg_val oldi_mode_reg_val; > }; > > static const struct dispc_bus_format dispc_bus_formats[] = { > - { MEDIA_BUS_FMT_RGB444_1X12, 12, false, 0 }, > - { MEDIA_BUS_FMT_RGB565_1X16, 16, false, 0 }, > - { MEDIA_BUS_FMT_RGB666_1X18, 18, false, 0 }, > - { MEDIA_BUS_FMT_RGB888_1X24, 24, false, 0 }, > - { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, 0 }, > - { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, 0 }, > - { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, SPWG_18 }, > - { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, SPWG_24 }, > - { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, JEIDA_24 }, > + { MEDIA_BUS_FMT_RGB444_1X12, 12, false, false, 0 }, > + { MEDIA_BUS_FMT_RGB565_1X16, 16, false, false, 0 }, > + { MEDIA_BUS_FMT_RGB666_1X18, 18, false, false, 0 }, > + { MEDIA_BUS_FMT_RGB888_1X24, 24, false, false, 0 }, > + { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, false, 0 }, > + { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, false, 0 }, > + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, false, SPWG_18 }, > + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, false, SPWG_24 }, > + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, false, JEIDA_24 }, > + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, true, DL_SPWG_18 }, > + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, true, DL_SPWG_24 }, > + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, true, DL_JEIDA_24 }, > };
So the dual link sends two pixels per clock, right? Are there panel or bridge drivers that support this? My initial thought was that it should be a new bus format.
Tomi
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