Messages in this thread | | | Date | Mon, 18 Jul 2022 18:00:54 +0200 | From | Mauro Carvalho Chehab <> | Subject | Re: [Intel-gfx] [PATCH v2 04/21] drm/i915/gt: Only invalidate TLBs exposed to user manipulation |
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On Mon, 18 Jul 2022 14:39:17 +0100 Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 14/07/2022 13:06, Mauro Carvalho Chehab wrote: > > From: Chris Wilson <chris.p.wilson@intel.com> > > > > Don't flush TLBs when the buffer is only used in the GGTT under full > > control of the kernel, as there's no risk of concurrent access > > and stale access from prefetch. > > > > We only need to invalidate the TLB if they are accessible by the user. > > That helps to reduce the performance regression introduced by TLB > > invalidate logic. > > > > Cc: stable@vger.kernel.org > > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > > Do we really need or want stable and fixes on this one? > > What do we think the performance improvement is, given there's very > little in GGTT, which is not mapped via PPGTT as well? > > I think it is safe, but part of me would ideally not even want to think > about whether it is safe, if the performance improvement is > non-existent. Which I can't imagine how there would be?
Makes sense. Patch 6 actually ends removing the code doing that, so I'll just fold this patch with patch 6, in order to avoid adding something that will later be removed.
Regards, Mauro
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