This adds support for CRS-based rate adaptation, such as the type used
for 10PASS-TS and 2BASE-TL. As these link modes are not supported by any
in-tree phy, this patch is marked as RFC. It serves chiefly to
illustrate the approach to adding support for another rate adaptation
type.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

Changes in v3:
- New

 drivers/net/phy/phylink.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 7f65413aa778..d27f6d23861c 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -476,7 +476,15 @@ void phylink_get_linkmodes(unsigned long *linkmodes, phy_interface_t interface,
 		break;
 	}
 	case RATE_ADAPT_CRS:
-		/* TODO */
+		/* We can only adapt if the MAC supports half-duplex at the
+		 * interface speed
+		 */
+		if (caps & MAC_1000) {
+			if (mac_capabilities & MAC_1000HD)
+				caps |= MAC_100 | MAC_10;
+		} else if (caps & MAC_100 && mac_capabilities & MAC_100HD) {
+			caps |= MAC_10;
+		}
 		break;
 	case RATE_ADAPT_OPEN_LOOP:
 open_loop:
@@ -1448,6 +1456,8 @@ static void phylink_phy_change(struct phy_device *phydev, bool up)
 	if (phydev->rate_adaptation == RATE_ADAPT_PAUSE) {
 		pl->phy_state.duplex = DUPLEX_FULL;
 		rx_pause = true;
+	} else if (phydev->rate_adaptation == RATE_ADAPT_CRS) {
+		pl->phy_state.duplex = DUPLEX_HALF;
 	}
 	pl->phy_state.pause = MLO_PAUSE_NONE;
 	if (tx_pause)
-- 
2.35.1.1320.gc452695387.dirty