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    SubjectRe: [PATCH v14 03/17] PCI: imx6: Move imx6_pcie_enable_ref_clk() earlier
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    Am Freitag, dem 01.07.2022 um 11:25 +0800 schrieb Richard Zhu:
    > From: Bjorn Helgaas <bhelgaas@google.com>
    >
    > Move imx6_pcie_enable_ref_clk() earlier so it's not in the middle between
    > imx6_pcie_assert_core_reset() and imx6_pcie_deassert_core_reset(). No
    > functional change intended.
    >
    > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    > Acked-by: Richard Zhu <hongxing.zhu@nxp.com>

    Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

    > ---
    > drivers/pci/controller/dwc/pci-imx6.c | 96 +++++++++++++--------------
    > 1 file changed, 48 insertions(+), 48 deletions(-)
    >
    > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
    > index e63eb6380020..a6d2b907d42b 100644
    > --- a/drivers/pci/controller/dwc/pci-imx6.c
    > +++ b/drivers/pci/controller/dwc/pci-imx6.c
    > @@ -520,54 +520,6 @@ static int imx6_pcie_attach_pd(struct device *dev)
    > return 0;
    > }
    >
    > -static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
    > -{
    > - struct device *dev = imx6_pcie->pci->dev;
    > -
    > - switch (imx6_pcie->drvdata->variant) {
    > - case IMX7D:
    > - case IMX8MQ:
    > - reset_control_assert(imx6_pcie->pciephy_reset);
    > - fallthrough;
    > - case IMX8MM:
    > - reset_control_assert(imx6_pcie->apps_reset);
    > - break;
    > - case IMX6SX:
    > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
    > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
    > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
    > - /* Force PCIe PHY reset */
    > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
    > - IMX6SX_GPR5_PCIE_BTNRST_RESET,
    > - IMX6SX_GPR5_PCIE_BTNRST_RESET);
    > - break;
    > - case IMX6QP:
    > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
    > - IMX6Q_GPR1_PCIE_SW_RST,
    > - IMX6Q_GPR1_PCIE_SW_RST);
    > - break;
    > - case IMX6Q:
    > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
    > - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
    > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
    > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
    > - break;
    > - }
    > -
    > - if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
    > - int ret = regulator_disable(imx6_pcie->vpcie);
    > -
    > - if (ret)
    > - dev_err(dev, "failed to disable vpcie regulator: %d\n",
    > - ret);
    > - }
    > -
    > - /* Some boards don't have PCIe reset GPIO. */
    > - if (gpio_is_valid(imx6_pcie->reset_gpio))
    > - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
    > - imx6_pcie->gpio_active_high);
    > -}
    > -
    > static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
    > {
    > struct dw_pcie *pci = imx6_pcie->pci;
    > @@ -628,6 +580,54 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
    > return ret;
    > }
    >
    > +static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
    > +{
    > + struct device *dev = imx6_pcie->pci->dev;
    > +
    > + switch (imx6_pcie->drvdata->variant) {
    > + case IMX7D:
    > + case IMX8MQ:
    > + reset_control_assert(imx6_pcie->pciephy_reset);
    > + fallthrough;
    > + case IMX8MM:
    > + reset_control_assert(imx6_pcie->apps_reset);
    > + break;
    > + case IMX6SX:
    > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
    > + IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
    > + IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
    > + /* Force PCIe PHY reset */
    > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
    > + IMX6SX_GPR5_PCIE_BTNRST_RESET,
    > + IMX6SX_GPR5_PCIE_BTNRST_RESET);
    > + break;
    > + case IMX6QP:
    > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
    > + IMX6Q_GPR1_PCIE_SW_RST,
    > + IMX6Q_GPR1_PCIE_SW_RST);
    > + break;
    > + case IMX6Q:
    > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
    > + IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
    > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
    > + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
    > + break;
    > + }
    > +
    > + if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
    > + int ret = regulator_disable(imx6_pcie->vpcie);
    > +
    > + if (ret)
    > + dev_err(dev, "failed to disable vpcie regulator: %d\n",
    > + ret);
    > + }
    > +
    > + /* Some boards don't have PCIe reset GPIO. */
    > + if (gpio_is_valid(imx6_pcie->reset_gpio))
    > + gpio_set_value_cansleep(imx6_pcie->reset_gpio,
    > + imx6_pcie->gpio_active_high);
    > +}
    > +
    > static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
    > {
    > struct dw_pcie *pci = imx6_pcie->pci;
    > --
    > 2.25.1
    >


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