Messages in this thread Patch in this message | | | From | Julian Haller <> | Subject | [PATCH 4/4] dt-bindings: w1: Add schema for Maxim DS1WM | Date | Thu, 30 Jun 2022 13:26:51 +0200 |
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From: Julian Haller <julian.haller@philips.com>
The Maxim DS1WM is a synthesizable 1-Wire Bus Master for usage in custom ASIC and FPGA designs. The datatsheet can be found under https://datasheets.maximintegrated.com/en/ds/DS1WM.pdf
Signed-off-by: Julian Haller <julian.haller@philips.com> --- .../devicetree/bindings/w1/maxim,ds1wm.yaml | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/w1/maxim,ds1wm.yaml
diff --git a/Documentation/devicetree/bindings/w1/maxim,ds1wm.yaml b/Documentation/devicetree/bindings/w1/maxim,ds1wm.yaml new file mode 100644 index 000000000000..c3f57ff2fdde --- /dev/null +++ b/Documentation/devicetree/bindings/w1/maxim,ds1wm.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/w1/maxim,ds1wm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim DS1WM One wire bus master controller Binding + +maintainers: + - Evgeniy Polyakov <zbr@ioremap.net> + +description: | + This document describes bindings which can be used to + describe DS1WM devices in a device tree. The DS1WM is a synthesizable 1-Wire + Bus Master for usage in custom ASIC and FPGA designs. + + The datatsheet can be found under + https://datasheets.maximintegrated.com/en/ds/DS1WM.pdf + +properties: + $nodename: + pattern: "^w1(@.*|-[0-9a-f])*$" + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + compatible: + const: maxim,ds1wm + + maxim,clock-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + DS1WM input clock rate. + + maxim,active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: + When set, INTR pin is active high. Defaults to active low. + + maxim,register-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + DS1WM register size in bytes. + oneOf: + - enum: [1, 2, 4] + + maxim,reset-recover-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Amount of time to sleep following a reset pulse (in milliseconds). Zero + should work if your bus devices recover time respects the 1-wire spec + since the ds1wm implements the precise timings of a reset pulse/presence + detect sequence. + + maxim,big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: + Set if DS1WM hardware is of type big-endian. Defaults to little-endian. + + maxim,strong-pullup-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enables the strong pull-up output enable (STPZ) pin’s functionality which + allows an external strong pull-up any time the master is not pulling the + line low or waiting to read a value from a slave device. This + functionality is used for meeting the recovery time requirement in + Overdrive mode and long-line standard communications. + + maxim,strong-pullup-supply: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enables the STPZ output while the master is in an IDLE state. This will + provide a stiff supply to devices requiring high current during + operations. Requires maxim,strong-pullup-enable. + +required: + - compatible + - reg + - interrupts + - maxim,register-size + - maxim,reset-recover-delay + - maxim,clock-rate + +additionalProperties: false + +examples: + - | + w1@4200 { + compatible = "maxim,ds1wm"; + reg = <0x4200 0x24>; + interrupts = <10>; + maxim,register-size = <4>; + maxim,reset-recover-delay = <2>; + maxim,clock-rate = <100000000>; + maxim,strong-pullup; + maxim,big-endian; + maxim,active-high; + }; +... -- 2.25.1
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