Messages in this thread | | | Date | Thu, 30 Jun 2022 06:28:30 +0200 | From | Christoph Hellwig <> | Subject | Re: [PATCH v5 3/4] riscv: Implement Zicbom-based cache management operations |
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On Wed, Jun 29, 2022 at 11:59:43PM +0200, Heiko Stuebner wrote: > The Zicbom ISA-extension was ratified in november 2021 > and introduces instructions for dcache invalidate, clean > and flush operations. > > Implement cache management operations based on them. > > Of course not all cores will support this, so implement an > alternative-based mechanism that replaces empty instructions > with ones done around Zicbom instructions. > > As discussed in previous versions, assume the platform > being coherent by default so that non-coherent devices need > to get marked accordingly by firmware.
The subject here seems somewhat odd. Yes, it does implement the low-level cache management ops, but more importantly it adds support for devices that are not DMA coherent.
Otherwise looks good:
Reviewed-by: Christoph Hellwig <hch@lst.de>
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