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    Subject[PATCH v2 05/12] irqchip: mips-gic: Setup defaults in each cluster
    Date
    From: Chao-ying Fu <cfu@wavecomp.com>

    In multi-cluster MIPS I6500 systems we have a GIC per cluster. The
    default shared interrupt setup that we configure in gic_of_init() will
    only apply to the GIC in the cluster containing the boot CPU, leaving
    the GICs of other clusters unconfigured. Similarly configure other
    clusters here.

    Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
    Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>

    diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
    index 89a3c6d04e09..f692392666a2 100644
    --- a/drivers/irqchip/irq-mips-gic.c
    +++ b/drivers/irqchip/irq-mips-gic.c
    @@ -741,7 +741,7 @@ static int gic_cpu_startup(unsigned int cpu)
    static int __init gic_of_init(struct device_node *node,
    struct device_node *parent)
    {
    - unsigned int cpu_vec, i, gicconfig, v[2], num_ipis;
    + unsigned int cpu_vec, i, gicconfig, v[2], num_ipis, cl, nclusters;
    unsigned long reserved;
    phys_addr_t gic_base;
    struct resource res;
    @@ -860,11 +860,30 @@ static int __init gic_of_init(struct device_node *node,

    board_bind_eic_interrupt = &gic_bind_eic_interrupt;

    - /* Setup defaults */
    - for (i = 0; i < gic_shared_intrs; i++) {
    - change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
    - change_gic_trig(i, GIC_TRIG_LEVEL);
    - write_gic_rmask(i);
    + /*
    + * Initialise each cluster's GIC shared registers to sane default
    + * values.
    + * Otherwise, the IPI set up will be erased if we move code
    + * to gic_cpu_startup for each cpu.
    + */
    + nclusters = mips_cps_numclusters();
    + for (cl = 0; cl < nclusters; cl++) {
    + if (cl == cpu_cluster(&current_cpu_data)) {
    + for (i = 0; i < gic_shared_intrs; i++) {
    + change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
    + change_gic_trig(i, GIC_TRIG_LEVEL);
    + write_gic_rmask(i);
    + }
    + } else {
    + mips_cm_lock_other(cl, 0, 0,
    + CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
    + for (i = 0; i < gic_shared_intrs; i++) {
    + change_gic_redir_pol(i, GIC_POL_ACTIVE_HIGH);
    + change_gic_redir_trig(i, GIC_TRIG_LEVEL);
    + write_gic_redir_rmask(i);
    + }
    + mips_cm_unlock_other();
    + }
    }

    return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
    --
    2.17.1
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