lkml.org 
[lkml]   [2022]   [May]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH 0/2] hyperv compose_msi_msg fixups
On Mon, May 09, 2022 at 03:48:20PM -0600, Jeffrey Hugo wrote:
> While multi-MSI appears to work with pci-hyperv.c, there was a concern about
> how linux was doing the ITRE allocations. Patch 2 addresses the concern.
>
> However, patch 2 exposed an issue with how compose_msi_msg() was freeing a
> previous allocation when called for the Nth time. Imagine a driver using
> pci_alloc_irq_vectors() to request 32 MSIs. This would cause compose_msi_msg()
> to be called 32 times, once for each MSI. With patch 2, MSI0 would allocate
> the ITREs needed, and MSI1-31 would use the cached information. Then the driver
> uses request_irq() on MSI1-17. This would call compose_msi_msg() again on those
> MSIs, which would again use the cached information. Then unmask() would be
> called to retarget the MSIs to the right VCPU vectors. Finally, the driver
> calls request_irq() on MSI0. This would call conpose_msi_msg(), which would
> free the block of 32 MSIs, and allocate a new block. This would undo the
> retarget of MSI1-17, and likely leave those MSIs targeting invalid VCPU vectors.
> This is addressed by patch 1, which is introduced first to prevent a regression.
>
> Jeffrey Hugo (2):
> PCI: hv: Reuse existing ITRE allocation in compose_msi_msg()
> PCI: hv: Fix interrupt mapping for multi-MSI
>

Applied to hyperv-next. Thanks.

\
 
 \ /
  Last update: 2022-05-11 16:42    [W:0.188 / U:0.136 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site