Messages in this thread | | | From | Thomas Gleixner <> | Subject | RE: [PATCH] x86: Prefer MWAIT over HALT on AMD processors | Date | Wed, 06 Apr 2022 03:44:18 +0200 |
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Mario,
On Tue, Apr 05 2022 at 20:40, Mario Limonciello wrote:
> [Public]
Really useful information that your post is public while some of the earlier posts in this _public_ thread were marked '[AMD confidential]'.
>> >> This seem _bit_ at odds with the commit message (and the AMD SSBD >> >> whitepaper): >> >> >> >>> Add the necessary synchronization logic for AMD family 17H. >> >> So, is X86_FEATURE_ZEN for family==0x17, or family>=0x17? >> > There are Zen family CPUs and APUs from family 0x19. Perhaps at the >> > time of the whitepaper there weren't yet though. >> >> Is this a gap in the documentation, then? Is there some documentation >> of the availability of SSBD mitigations on family 0x19? > > It looks like a misinterpretation of the document.
Not at all. The document does not mention family 19h at all. So where is the misinterpretation?
Dave was asking for documentation for family 0x19, right?
> Notice it mentions in Non-architectural MSRs explicitly: > > "some models of family 17h have logic that allow loads to bypass older stores > but lack the architectural SPEC_CTRL or VIRT_SPEC_CTR"
That's relevant to Dave's question in which way?
> But that is not for all family 17h nor for family 19h. You can see earlier in > the document the method to detect presence for SSBD which applies to the > rest of 17h and 19h.
We know how to read this document. But this document does not mention anything else than family 17h. So what are you talking about?
> That code in amd_set_core_ssb_state is only used for one of the > mitigation codepaths without MSR support, not for all Zen CPUs.
Again, how is that relevant to the legitimate question whether that document applies to family 17h only or to 17h+ which includes 19h?
We need to make a decison about what X86_FEATURE_ZEN means. Is it that hard to give an authoritive answer?
Thanks,
tglx
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