Messages in this thread Patch in this message | | | From | Ashish Mhetre <> | Subject | [Patch v6 3/4] dt-bindings: memory: Update reg maxitems for tegra186 | Date | Wed, 6 Apr 2022 10:54:58 +0530 |
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From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each. There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation.
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> --- .../memory-controllers/nvidia,tegra186-mc.yaml | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 13c4c82fd0d3..0fe396a2e162 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -35,7 +35,7 @@ properties: reg: minItems: 1 - maxItems: 3 + maxItems: 18 interrupts: items: @@ -142,7 +142,8 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers - if: properties: @@ -152,6 +153,7 @@ allOf: properties: reg: minItems: 3 + description: 17 memory controller channels and 1 for stream-id registers - if: properties: @@ -161,6 +163,7 @@ allOf: properties: reg: minItems: 3 + description: 17 memory controller channels and 1 for stream-id registers additionalProperties: false @@ -182,7 +185,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <2>; -- 2.17.1
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