Messages in this thread | | | Subject | Re: [PATCH v2] clk: qcom: rcg2: Cache CFG register updates for parked RCGs | From | Stephen Boyd <> | Date | Mon, 04 Apr 2022 13:16:49 -0700 |
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Quoting Bjorn Andersson (2022-03-07 20:03:48) > As GDSCs are turned on and off some associated clocks are momentarily > enabled for house keeping purposes. For this, and similar, purposes the > "shared RCGs" will park the RCG on a source clock which is known to be > available. > When the RCG is parked, a safe clock source will be selected and > committed, then the original source would be written back and upon enable > the change back to the unparked source would be committed. > > But starting with SM8350 this fails, as the value in CFG is committed by > the GDSC handshake and without a valid parent the GDSC enablement will > fail. > > To avoid this problem, the software needs to cache the CFG register > content while the shared RCG is parked. > > Writes to M, N and D registers are committed as they are requested. New > helpers for get_parent() and recalc_rate() are extracted from their > previous implementations and __clk_rcg2_configure() is modified to allow > it to operate on the cached value. > > Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed") > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > ---
Sorry I've been delaying reviewing this patch. I'll review it in the next couple days.
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