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SubjectRe: [PATCH RFC 2/5] arm64: dts: qcom: sc7280: move pipe mux handling to phy
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On 21/04/2022 13:20, Johan Hovold wrote:
> The QMP PHY pipe clock remuxing is part of the PHY, which is both the
> producer and the consumer of the pipe clock.
>
> Update the PCIe controller and PHY node to reflect the new binding.
>
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 18 ++++++------------
> 1 file changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index c07765df9303..b3a9630262dc 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1837,11 +1837,7 @@ pcie1: pci@1c08000 {
> <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
> <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
>
> - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> - <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
> - <&pcie1_lane 0>,
> - <&rpmhcc RPMH_CXO_CLK>,
> - <&gcc GCC_PCIE_1_AUX_CLK>,
> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> @@ -1849,11 +1845,7 @@ pcie1: pci@1c08000 {
> <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
> <&gcc GCC_DDRSS_PCIE_SF_CLK>;
>
> - clock-names = "pipe",
> - "pipe_mux",
> - "phy_pipe",
> - "ref",
> - "aux",
> + clock-names = "aux",
> "cfg",
> "bus_master",
> "bus_slave",
> @@ -1910,8 +1902,10 @@ pcie1_lane: lanes@1c0e200 {
> <0 0x01c0e600 0 0x170>,
> <0 0x01c0e800 0 0x200>,
> <0 0x01c0ee00 0 0xf4>;
> - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
> - clock-names = "pipe0";
> + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "pipe0", "mux", "ref";

This will not be compatible with earlier DTB files, which was a problem
up to now.

>
> #phy-cells = <0>;
> #clock-cells = <1>;


--
With best wishes
Dmitry

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