| Date | Thu, 21 Apr 2022 11:08:05 +0200 | Subject | Re: [PATCH V2 01/12] clk: mediatek: reset: Fix written reset bit offset | From | AngeloGioacchino Del Regno <> |
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Il 20/04/22 15:05, Rex-BC Chen ha scritto: > Original assert/deassert bit is BIT(0), but it's more resonable to modify > them to BIT(id % 32) which is based on id. > > This patch will not influence any previous driver because the reset is > only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. > > Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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