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    Subject[PATCH v3 0/2] Add support for Xilinx Versal CPM5 Root Port
    Date
    Xilinx Versal Premium series has CPM5 block which supports Root Port
    functioning at Gen5 speed.

    Xilinx Versal CPM5 has few changes with existing CPM block.
    - CPM5 has dedicated register space for control and status registers.
    - CPM5 legacy interrupt handling needs additonal register bit
    to enable and handle legacy interrupts.

    Changes in v3:
    - consistency in is_cpm5 flag check expression.

    Bharat Kumar Gogada (2):
    dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
    PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

    .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++---
    drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++-
    2 files changed, 72 insertions(+), 8 deletions(-)

    --
    2.17.1

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