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    SubjectRe: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes
    On Fri, Mar 18, 2022 at 10:45:24PM +0800, Allen-KH Cheng wrote:
    > Add mmc nodes for mt8192 SoC.
    >
    > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
    > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

    Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

    > ---
    > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
    > 1 file changed, 30 insertions(+), 4 deletions(-)
    >
    > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
    > index 6220d6962f58..2648f2847993 100644
    > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
    > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
    > @@ -1150,10 +1150,36 @@
    > #clock-cells = <1>;
    > };
    >
    > - msdc: clock-controller@11f60000 {
    > - compatible = "mediatek,mt8192-msdc";
    > - reg = <0 0x11f60000 0 0x1000>;
    > - #clock-cells = <1>;
    > + mmc0: mmc@11f60000 {
    > + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
    > + reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
    > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
    > + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
    > + <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
    > + <&msdc_top CLK_MSDC_TOP_SRC_0P>,
    > + <&msdc_top CLK_MSDC_TOP_P_CFG>,
    > + <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
    > + <&msdc_top CLK_MSDC_TOP_AXI>,
    > + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
    > + clock-names = "source", "hclk", "source_cg", "sys_cg",
    > + "pclk_cg", "axi_cg", "ahb_cg";
    > + status = "disabled";
    > + };
    > +
    > + mmc1: mmc@11f70000 {
    > + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
    > + reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
    > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
    > + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
    > + <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
    > + <&msdc_top CLK_MSDC_TOP_SRC_1P>,
    > + <&msdc_top CLK_MSDC_TOP_P_CFG>,
    > + <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
    > + <&msdc_top CLK_MSDC_TOP_AXI>,
    > + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
    > + clock-names = "source", "hclk", "source_cg", "sys_cg",
    > + "pclk_cg", "axi_cg", "ahb_cg";
    > + status = "disabled";
    > };
    >
    > mfgcfg: clock-controller@13fbf000 {
    > --
    > 2.18.0
    >
    >

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