Messages in this thread Patch in this message | | | From | Kohei Tarumizu <> | Subject | [PATCH v2 6/8] x86: Add hardware prefetch control support for x86 | Date | Fri, 11 Mar 2022 19:19:38 +0900 |
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This adds module init/exit code, and creates sysfs attribute file "hardware_prefetcher_enable", "ip_prefetcher_enable" and "adjacent_cache_line_prefetcher_enable" for x86. This driver works only if the model is INTEL_FAM6_BROADWELL_X at this point.
If you would like to support a new model with the same register specifications as INTEL_FAM6_BROADWELL_X, it is possible to add the model settings to array of broadwell_cpu_ids[].
The details of the registers to be read and written in this patch are described below:
"https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html" Volume 4
Signed-off-by: Kohei Tarumizu <tarumizu.kohei@fujitsu.com> --- arch/x86/kernel/cpu/pfctl.c | 314 ++++++++++++++++++++++++++++++++++++ 1 file changed, 314 insertions(+) create mode 100644 arch/x86/kernel/cpu/pfctl.c
diff --git a/arch/x86/kernel/cpu/pfctl.c b/arch/x86/kernel/cpu/pfctl.c new file mode 100644 index 000000000000..be2dce644808 --- /dev/null +++ b/arch/x86/kernel/cpu/pfctl.c @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 FUJITSU LIMITED + * + * x86 Hardware Prefetch Control support + */ + +#include <linux/bitfield.h> +#include <linux/cacheinfo.h> +#include <linux/pfctl.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <asm/cpu_device_id.h> +#include <asm/intel-family.h> +#include <asm/msr.h> + +struct pfctl_driver x86_pfctl_driver; + +/************************************** + * Intle BROADWELL support + **************************************/ + +/* + * The register specification for each bits of Intel BROADWELL is as + * follow: + * + * [0] L2 Hardware Prefetcher Disable (R/W) + * [1] L2 Adjacent Cache Line Prefetcher Disable (R/W) + * [2] DCU Hardware Prefetcher Disable (R/W) + * [3] DCU IP Prefetcher Disable (R/W) + * [63:4] Reserved + * + * See "Intel 64 and IA-32 Architectures Software Developer's Manual" + * (https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html) + * for register specification details. + */ +#define BROADWELL_L2_HWPF_FIELD BIT_ULL(0) +#define BROADWELL_L2_ACLPF_FIELD BIT_ULL(1) +#define BROADWELL_DCU_HWPF_FIELD BIT_ULL(2) +#define BROADWELL_DCU_IPPF_FIELD BIT_ULL(3) + +static int broadwell_get_hwpf_enable(u64 reg, unsigned int level) +{ + u64 val; + + switch (level) { + case 1: + val = FIELD_GET(BROADWELL_DCU_HWPF_FIELD, reg); + break; + case 2: + val = FIELD_GET(BROADWELL_L2_HWPF_FIELD, reg); + break; + default: + return -EINVAL; + } + + if (val == 0) + return PFCTL_ENABLE_VAL; + else if (val == 1) + return PFCTL_DISABLE_VAL; + else + return -EINVAL; +} + +static int broadwell_modify_hwpf_enable(u64 *reg, unsigned int level, u64 val) +{ + if (val == PFCTL_ENABLE_VAL) + val = 0; + else + val = 1; + + switch (level) { + case 1: + *reg &= ~BROADWELL_DCU_HWPF_FIELD; + *reg |= FIELD_PREP(BROADWELL_DCU_HWPF_FIELD, val); + break; + case 2: + *reg &= ~BROADWELL_L2_HWPF_FIELD; + *reg |= FIELD_PREP(BROADWELL_L2_HWPF_FIELD, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int broadwell_get_ippf_enable(u64 reg, unsigned int level) +{ + u64 val; + + switch (level) { + case 1: + val = FIELD_GET(BROADWELL_DCU_IPPF_FIELD, reg); + break; + default: + return -EINVAL; + } + + if (val == 0) + return PFCTL_ENABLE_VAL; + else if (val == 1) + return PFCTL_DISABLE_VAL; + else + return -EINVAL; +} + +static int broadwell_modify_ippf_enable(u64 *reg, unsigned int level, u64 val) +{ + if (val == PFCTL_ENABLE_VAL) + val = 0; + else + val = 1; + + switch (level) { + case 1: + *reg &= ~BROADWELL_DCU_IPPF_FIELD; + *reg |= FIELD_PREP(BROADWELL_DCU_IPPF_FIELD, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int broadwell_get_aclpf_enable(u64 reg, unsigned int level) +{ + u64 val; + + switch (level) { + case 2: + val = FIELD_GET(BROADWELL_L2_ACLPF_FIELD, reg); + break; + default: + return -EINVAL; + } + + if (val == 0) + return PFCTL_ENABLE_VAL; + else if (val == 1) + return PFCTL_DISABLE_VAL; + else + return -EINVAL; +} + +static int broadwell_modify_aclpf_enable(u64 *reg, unsigned int level, u64 val) +{ + if (val == PFCTL_ENABLE_VAL) + val = 0; + else + val = 1; + + switch (level) { + case 2: + *reg &= ~BROADWELL_L2_ACLPF_FIELD; + *reg |= FIELD_PREP(BROADWELL_L2_ACLPF_FIELD, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int broadwell_get_pfctl_params(enum pfctl_attr pattr, u64 reg, + unsigned int level, u64 *val) +{ + int ret; + + switch (pattr) { + case HWPF_ENABLE: + ret = broadwell_get_hwpf_enable(reg, level); + break; + case IPPF_ENABLE: + ret = broadwell_get_ippf_enable(reg, level); + break; + case ACLPF_ENABLE: + ret = broadwell_get_aclpf_enable(reg, level); + break; + default: + return -ENOENT; + } + + if (ret < 0) + return ret; + *val = ret; + + return 0; +} + +static int broadwell_modify_pfreg(enum pfctl_attr pattr, u64 *reg, + unsigned int level, u64 val) +{ + int ret; + + switch (pattr) { + case HWPF_ENABLE: + ret = broadwell_modify_hwpf_enable(reg, level, val); + break; + case IPPF_ENABLE: + ret = broadwell_modify_ippf_enable(reg, level, val); + break; + case ACLPF_ENABLE: + ret = broadwell_modify_aclpf_enable(reg, level, val); + break; + default: + return -ENOENT; + } + + if (ret < 0) + return ret; + + return 0; +} + +static int broadwell_read_pfreg(enum pfctl_attr pattr, unsigned int cpu, + unsigned int level, u64 *val) +{ + int ret; + u64 reg; + + ret = rdmsrl_on_cpu(cpu, MSR_MISC_FEATURE_CONTROL, ®); + if (ret) + return ret; + + ret = broadwell_get_pfctl_params(pattr, reg, level, val); + if (ret) + return ret; + + return 0; +} + +static int broadwell_write_pfreg(enum pfctl_attr pattr, unsigned int cpu, + unsigned int level, u64 val) +{ + int ret; + u64 reg; + + ret = rdmsrl_on_cpu(cpu, MSR_MISC_FEATURE_CONTROL, ®); + if (ret) + return ret; + + ret = broadwell_modify_pfreg(pattr, ®, level, val); + if (ret < 0) + return ret; + + ret = wrmsrl_on_cpu(cpu, MSR_MISC_FEATURE_CONTROL, reg); + if (ret) + return ret; + + return 0; +} + +/* + * In addition to BROADWELL_X, NEHALEM and others have same register + * specifications as those represented by BROADWELL_XXX_FIELD. + * If you want to add support for these processor, add the new target model + * here. + */ +static const struct x86_cpu_id broadwell_cpu_ids[] = { + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, NULL), + {} +}; + +/***** end of Intel BROADWELL support *****/ + +/* + * This driver returns a negative value if it does not support the Hardware + * Prefetch Control or if it is running on a VM guest. + */ +static int __init setup_pfctl_driver_params(void) +{ + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) + return -EINVAL; + + if (x86_match_cpu(broadwell_cpu_ids)) { + x86_pfctl_driver.supported_l1d_prefetcher = HWPF|IPPF; + x86_pfctl_driver.supported_l2_prefetcher = HWPF|ACLPF; + x86_pfctl_driver.read_pfreg = broadwell_read_pfreg; + x86_pfctl_driver.write_pfreg = broadwell_write_pfreg; + } else { + return -ENODEV; + } + + return 0; +} + +static int __init x86_pfctl_init(void) +{ + int ret; + + ret = setup_pfctl_driver_params(); + if (ret < 0) + return ret; + + ret = pfctl_register_driver(&x86_pfctl_driver); + if (ret < 0) + return ret; + + return 0; +} + +static void __exit x86_pfctl_exit(void) +{ + pfctl_unregister_driver(&x86_pfctl_driver); +} + +late_initcall(x86_pfctl_init); +module_exit(x86_pfctl_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("FUJITSU LIMITED"); +MODULE_DESCRIPTION("x86 Hardware Prefetch Control Driver"); -- 2.27.0
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