lkml.org 
[lkml]   [2022]   [Mar]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    From
    Subject[PATCH v2 0/6] spi-mem: Allow specifying the byte order in DTR mode
    Date
    There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary
    when configured in Octal DTR mode. The byte order of 16-bit words is
    swapped when read or written in Octal Double Transfer Rate (DTR) mode
    compared to Single Transfer Rate (STR) modes. If one writes D0 D1 D2 D3
    bytes using 1-1-1 mode, and uses 8D-8D-8D SPI mode for reading, it will
    read back D1 D0 D3 D2. Swapping the bytes is a bad design decision because
    it may introduce some endianness problems. It can affect the boot sequence
    if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1
    mode. So we must swap the bytes back to have the same byte order as in STR
    modes. Fortunately there are controllers that can swap the bytes back at
    runtime, addressing the flash's endiannesses requirements.
    If the controllers are not capable of swapping the bytes, the protocol is
    downgraded via spi_nor_spimem_adjust_hwcaps(). When available, the swapping
    of the bytes is always done regardless if it's a data or register access,
    so that we comply with the JESD216 requirements: "Byte order of 16-bit
    words is swapped when read in 8D-8D-8D mode compared to 1-1-1".

    Tested with atmel-quadspi driver, both in 8D-8D-8D mode and 1-1-1 mode
    (via the protocol downgrade).

    This patch set depends on the SPI MEM changes from linux-mtd/mtd/next and
    also on some SPI NOR patches that are waiting for R-b tags. You can find
    a branch if you want to test it at:

    To github.com:ambarus/linux-0day.git
    * [new branch] spi-nor/next-mx-byte-swap-v2 -> spi-nor/next-mx-byte-swap-v2

    v2:
    - all: s/bswap16/swab16 to comply with linux naming scheme
    - SPI MEM: add dtr_swab16 cap to spi_controller_mem_caps and update
    spi_mem_default_supports_op() to check for it.
    - SPI NOR: do not encode swab16 info in the SPI NOR protocol, use a helper
    instead
    - SPI NOR: downgrade the SPI NOR protocol in case the SPI Controller does
    not support swab16
    - add SPI_NOR_SOFT_RESET and support for mx66lm1g45g

    Tudor Ambarus (6):
    spi: spi-mem: Allow specifying the byte order in DTR mode
    mtd: spi-nor: core: Allow specifying the byte order in DTR mode
    mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT
    mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag
    mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag
    mtd: spi-nor: macronix: Add support for mx66lm1g45g

    drivers/mtd/spi-nor/core.c | 16 +++-
    drivers/mtd/spi-nor/core.h | 10 ++-
    drivers/mtd/spi-nor/macronix.c | 130 +++++++++++++++++++++++++++++++++
    drivers/mtd/spi-nor/sfdp.c | 4 +
    drivers/spi/spi-mem.c | 4 +
    include/linux/spi/spi-mem.h | 6 ++
    6 files changed, 168 insertions(+), 2 deletions(-)

    --
    2.25.1

    \
     
     \ /
      Last update: 2022-09-17 16:16    [W:5.402 / U:0.028 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site