Messages in this thread | | | Date | Mon, 7 Feb 2022 21:27:43 +0100 | From | Borislav Petkov <> | Subject | Re: [RFC] x86/mce: Add workaround for SKX/CLX/CPX spurious machine checks |
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On Mon, Feb 07, 2022 at 11:24:53AM -0800, Luck, Tony wrote: > I suggested breaking it out as a helper to make the > code easier to read.
We have waaay too many small helpers. I guess it is just as readable if you do in the function:
bool is_intel_srar = mci_status & (MCI_STATUS_VAL|MCI_STATUS_OVER|MCI_STATUS_UC|MCI_STATUS_EN| (MCI_STATUS_ADDRV|MCI_STATUS_MISCV|MCI_STATUS_PCC| MCI_STATUS_AR|MCI_STATUS_S)) == (MCI_STATUS_VAL|MCI_STATUS_UC|MCI_STATUS_EN|MCI_STATUS_ADDRV| MCI_STATUS_MISCV|MCI_STATUS_AR|MCI_STATUS_S);
> X86_FEATURE_FSRM is a different (but confusingly simlilar) feature. > > The MSR is per-thread. So the write only disabled the fast string > operation on this one logical CPU. So the per-cpu srar_dcu_signaled > variable is just to avoid getting into a loop when this #MC isn't > because of a REP MOVS peeking at things it shouldn't.
In that case, you can just as well test the MSR bit directly MSR_IA32_MISC_ENABLE_FAST_STRING_BIT. If it set, you clear it, done.
> Maybe this would be more human friendly? > > pr_err("CPU%d: Performance now degraded after applying machine check workaround\n", > smp_processor_id());
Well, is there an erratum you can refer to in it instead?
Explaining the whole deal in a single error message is hard and almost certainly insufficient.
Also, what's the use of that message issuing once on every CPU? Instead of being a _once() message?
Thx.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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