Messages in this thread | | | From | "Luck, Tony" <> | Subject | RE: [RFC PATCH 1/2] x86/mce: Handle AMD threshold interrupt storms | Date | Wed, 23 Feb 2022 23:03:21 +0000 |
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> It looks to me most of the code can be shared except in few places > where AMD and Intel use different registers to set error thresholds.
Hopefully easy to abstract.
> And the fact that AMD's threshold interrupts just handles corrected > errors unlike CMCI.
That makes your life much simpler than mine :-)
> I'm thinking of coming up with a shared code between both by keeping > the Intel's new storm handling code as base and incorporating AMD > changes on them and send for review. > > Let me know if thats okay?
My new Intel code hasn't had Boris look through it yet to point out all the bits where I have bugs, or just make things more complex than they need to be.
So it would be helpful if Boris could do at least a quick scan to say my code is a worthy base. I'd hate to see you waste time building a merged version and then have Boris say "Nack".
-Tony
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