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    SubjectRe: [PATCH v1 1/6] dt-bindings: i2c: npcm: support NPCM845
    On Mon, Feb 07, 2022 at 02:33:33PM +0800, Tyrone Ting wrote:
    > From: Tyrone Ting <kfting@nuvoton.com>
    >
    > This commit adds compatible and syscon description for NPCM845 i2c module.
    >
    > Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver")
    > Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
    > Signed-off-by: Tali Perry <tali.perry1@gmail.com>
    > ---
    > .../bindings/i2c/nuvoton,npcm7xx-i2c.yaml | 21 ++++++++++++++-----
    > 1 file changed, 16 insertions(+), 5 deletions(-)
    >
    > diff --git a/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
    > index 128444942aec..05e58f44b03a 100644
    > --- a/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
    > +++ b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
    > @@ -7,17 +7,22 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
    > title: nuvoton NPCM7XX I2C Controller Device Tree Bindings
    >
    > description: |
    > - The NPCM750x includes sixteen I2C bus controllers. All Controllers support
    > - both master and slave mode. Each controller can switch between master and slave
    > - at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and
    > - RX.
    > + The NPCM7XX includes sixteen I2C bus controllers and the NPCM8XX includes
    > + twenty-seven I2C bus controllers. NPCM8XX controllers 24-26 are connected on I2C
    > + pins in parallel to controllers 8-10.

    How many instances is really outside the scope of this binding. And I
    don't want to be updating this for every new SoC. So rework it to cover
    both chips and the next one.

    > + All controllers support both master and slave mode.
    > + Each controller can switch between master and slave at run time (i.e. IPMB mode).
    > + NPCM7XX I2C controller has two 16 byte HW FIFO for TX and RX and NPCM8XX I2C
    > + controller has two 32 byte HW FIFO for TX and RX.
    >
    > maintainers:
    > - Tali Perry <tali.perry1@gmail.com>
    >
    > properties:
    > compatible:
    > - const: nuvoton,npcm750-i2c
    > + enum:
    > + - nuvoton,npcm750-i2c
    > + - nuvoton,npcm845-i2c
    >
    > reg:
    > maxItems: 1
    > @@ -36,11 +41,16 @@ properties:
    > default: 100000
    > enum: [100000, 400000, 1000000]
    >
    > + syscon:

    nuvoton,sys-mgr or similar.

    > + $ref: "/schemas/types.yaml#/definitions/phandle"
    > + description: The phandle of system manager register node.
    > +
    > required:
    > - compatible
    > - reg
    > - interrupts
    > - clocks
    > + - syscon
    >
    > allOf:
    > - $ref: /schemas/i2c/i2c-controller.yaml#
    > @@ -57,6 +67,7 @@ examples:
    > clock-frequency = <100000>;
    > interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
    > compatible = "nuvoton,npcm750-i2c";
    > + syscon = <&gcr>;
    > };
    >
    > ...
    > --
    > 2.17.1
    >
    >

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