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SubjectRe: [PATCH 14/15] can: tcan4x5x: Fix register range of first block
On 05.12.2022 10:30:13, Markus Schneider-Pargmann wrote:
> Hi Marc,
>
> On Fri, Dec 02, 2022 at 03:28:10PM +0100, Marc Kleine-Budde wrote:
> > On 16.11.2022 21:53:07, Markus Schneider-Pargmann wrote:
> > > According to the datasheet 0x1c is the last register in the first block,
> > > not register 0x2c.
> >
> > The datasheet "SLLSF91A – DECEMBER 2018 – REVISED JANUARY 2020" says:
> >
> > | 8.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to
> > | 16'h002F
> >
> > While the last described register is at 0xc.
>
> Sorry, not sure what I looked up here. The last described register is
> 0x10 SPI Error status mask in my datasheet:
> 'SLLSEZ5D – JANUARY 2018 – REVISED JUNE 2022'

The TCAN4550-Q1 variant has the 0x10 register documented, while the
TCAN4550 (w/o -Q1) doesn't have.

> I would prefer using the actual registers if that is ok with you, so
> 0x10 here because I assume the remaining registers have internal use or
> maybe don't exist at all?! If there is an undocumented register that
> needs to be used at some point we can still modify the ranges.

I'm fine with using 0x10 as the last register.

> Also it seems the existing ranges are following the same logic and don't
> list the whole range, just the documented registers.
>
> The second range is wrong as well. The last register is 0x830, will
> fix.

IIRC I used the register ranges from the section titles ("8.6.1 Device
ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F") when
I added the {wr,rd}_table.

Marc

--
Pengutronix e.K. | Marc Kleine-Budde |
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