Messages in this thread |  | | Date | Sun, 25 Dec 2022 23:16:08 +0100 | | From | Marijn Suijten <> | | Subject | Re: [PATCH 2/5] arm64: dts: qcom: sm6125: re-order USB2 phy clocks |
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On 2022-12-24 16:42:52, Krzysztof Kozlowski wrote: > Bindings expect USB2 phy clocks in other order: > > sm6125-sony-xperia-seine-pdx201.dtb: phy@1613000: clock-names:1: 'ref' was expected > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This was already sent last week as:
https://lore.kernel.org/linux-arm-msm/20221216213343.1140143-1-marijn.suijten@somainline.org/
- Marijn
> --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index 7e25a4f85594..bf9e8d45ee44 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -442,9 +442,9 @@ hsusb_phy1: phy@1613000 { > reg = <0x01613000 0x180>; > #phy-cells = <0>; > > - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > - <&gcc GCC_AHB2PHY_USB_CLK>; > - clock-names = "ref", "cfg_ahb"; > + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "cfg_ahb", "ref"; > > resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > status = "disabled"; > -- > 2.34.1 >
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