Messages in this thread | | | Date | Fri, 2 Dec 2022 09:53:21 +0100 | From | Neil Armstrong <> | Subject | Re: [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D |
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On 01/12/2022 23:43, Martin Blumenstingl wrote: > On Thu, Dec 1, 2022 at 11:30 AM Tomeu Vizoso <tomeu.vizoso@collabora.com> wrote: >> >> Based on power initialization sequence in downstream driver. >> >> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> >> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> > Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > > [...] >> +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { >> + { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) }, >> + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) }, > I noticed the discussion in v1 of this series where Neil noted that > you should change GENMASK(31, 0) to GENMASK(23, 0) (for > G12A_HHI_NANOQ_MEM_PD_REG1). > This is all a bit confusing because the S905D3 datasheet mentions that > the HHI_NANOQ_MEM_PD_REG1 register uses the full 32 bits. > I'm still fine with the way it is right now because the datasheets are > not always perfect.
Yes they're different in G12B & SM1 Neil
> > > Best regards, > Martin
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