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    SubjectRe: [PATCH v4 12/39] x86/mm: Update ptep_set_wrprotect() and pmdp_set_wrprotect() for transition from _PAGE_DIRTY to _PAGE_COW
    On Fri, Dec 02, 2022 at 04:35:39PM -0800, Rick Edgecombe wrote:
    > From: Yu-cheng Yu <yu-cheng.yu@intel.com>
    >
    > When Shadow Stack is in use, Write=0,Dirty=1 PTE are reserved for shadow
    > stack. Copy-on-write PTes then have Write=0,Cow=1.
    >
    > When a PTE goes from Write=1,Dirty=1 to Write=0,Cow=1, it could
    > become a transient shadow stack PTE in two cases:
    >
    > The first case is that some processors can start a write but end up seeing
    > a Write=0 PTE by the time they get to the Dirty bit, creating a transient
    > shadow stack PTE. However, this will not occur on processors supporting
    > Shadow Stack, and a TLB flush is not necessary.
    >
    > The second case is that when _PAGE_DIRTY is replaced with _PAGE_COW non-
    > atomically, a transient shadow stack PTE can be created as a result.
    > Thus, prevent that with cmpxchg.
    >
    > In the case of pmdp_set_wrprotect(), for nopmd configs the ->pmd operated
    > on does not exist and the logic would need to be different. Although the
    > extra functionality will normally be optimized out when user shadow
    > stacks are not configured, also exclude it in the preprocessor stage so
    > that it will still compile. User shadow stack is not supported there by
    > Linux anyway. Leave the cpu_feature_enabled() check so that the
    > functionality also disables based on runtime detection of the feature.
    >
    > Dave Hansen, Jann Horn, Andy Lutomirski, and Peter Zijlstra provided many
    > insights to the issue. Jann Horn provided the cmpxchg solution.
    >
    > Tested-by: Pengfei Xu <pengfei.xu@intel.com>
    > Tested-by: John Allen <john.allen@amd.com>
    > Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>

    Reviewed-by: Kees Cook <keescook@chromium.org>

    --
    Kees Cook

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