Messages in this thread |  | | From | Geert Uytterhoeven <> | Date | Mon, 19 Dec 2022 14:50:36 +0100 | Subject | Re: [PATCH RFC 1/5] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC |
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Hi Prabhakar,
On Mon, Dec 19, 2022 at 1:57 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Fri, Nov 18, 2022 at 12:29 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Thu, Nov 17, 2022 at 10:54 AM Geert Uytterhoeven > > <geert@linux-m68k.org> wrote: > > > On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Document RZ/G2UL (R9A07G043) IRQC bindings. The RZ/G2UL IRQC block is > > > > identical to one found on the RZ/G2L SoC. No driver changes are > > > > required as generic compatible string "renesas,rzg2l-irqc" will be > > > > used as a fallback. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Note, renesas,r9a07g043u-irqc is added we have slight difference's compared to RZ/Five > > > > - G2UL IRQCHIP (hierarchical IRQ domain) -> GIC where as on RZ/Five we have PLIC (chained interrupt > > > > domain) -> RISCV INTC > > > > > > I think this difference is purely a software difference, and abstracted > > > in DTS through the interrupt hierarchy. > > > Does it have any impact on the bindings? > > > > > > > - On the RZ/Five we have additional registers for IRQC block > > > > > > Indeed, the NMI/IRQ/TINT "Interruput" Mask Control Registers, thus > > > warranting separate compatible values. > > > > > > > - On the RZ/Five we have BUS_ERR_INT which needs to be handled by IRQC > > > > > > Can you please elaborate? I may have missed something, but to me it > > > looks like that is exactly the same on RZ/G2UL and on RZ/Five. > > > > > Now that we have to update the binding doc with the BUS_ERR_INT too, > > do you think it would make sense to add interrupt-names too?
> Gentle ping.
Thanks for the ping, I had missed you were waiting on input from me. Sorry for that...
As there are three different groups of parent interrupts, adding interrupt-names makes sense. However, as this binding is already in active use since v6.1, you probably need to keep on supporting the ack of interrupt-names. Or do you think there are no real users yet, and we can drop support for that?
> > BUS_ERR_INT will have to be handled IRQC itself (i.e. IRQC will > > register a handler for it).
Do you mean you will need a fourth parent type for that?
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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