Messages in this thread Patch in this message |  | | From | Andy Shevchenko <> | Subject | [PATCH v1 1/1] pinctrl: intel: Use same order of bit fields for PADCFG2 | Date | Mon, 19 Dec 2022 14:32:29 +0200 |
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PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same for PADCFG2 bit fields.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- drivers/pinctrl/intel/pinctrl-intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 5e21b0a96efe..9d2791a81ffa 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -88,9 +88,9 @@ #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) #define PADCFG2 0x008 -#define PADCFG2_DEBEN BIT(0) #define PADCFG2_DEBOUNCE_SHIFT 1 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) +#define PADCFG2_DEBEN BIT(0) #define DEBOUNCE_PERIOD_NSEC 31250 -- 2.35.1
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