Messages in this thread Patch in this message |  | | From | Sean Anderson <> | Subject | [PATCH net-next v4 3/4] net: mdio: Update speed register bits | Date | Fri, 16 Dec 2022 11:48:50 -0500 |
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This updates the speed register bits to the 2018 revision of 802.3.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> ---
(no changes since v3)
Changes in v3: - New
include/uapi/linux/mdio.h | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h index 14b779a8577b..490466f9a5c5 100644 --- a/include/uapi/linux/mdio.h +++ b/include/uapi/linux/mdio.h @@ -147,6 +147,7 @@ #define MDIO_SPEED_10G 0x0001 /* 10G capable */ /* PMA/PMD Speed register. */ +#define MDIO_PMA_SPEED_10G MDIO_SPEED_10G #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */ #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */ #define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ @@ -154,9 +155,15 @@ #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ /* PCS et al. Speed register. */ +#define MDIO_PCS_SPEED_10G MDIO_SPEED_10G #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ +#define MDIO_PCS_SPEED_40G 0x0004 /* 450G capable */ +#define MDIO_PCS_SPEED_100G 0x0008 /* 100G capable */ +#define MDIO_PCS_SPEED_25G 0x0010 /* 25G capable */ #define MDIO_PCS_SPEED_2_5G 0x0040 /* 2.5G capable */ #define MDIO_PCS_SPEED_5G 0x0080 /* 5G capable */ +#define MDIO_PCS_SPEED_200G 0x0100 /* 200G capable */ +#define MDIO_PCS_SPEED_400G 0x0200 /* 400G capable */ /* Device present registers. */ #define MDIO_DEVS_PRESENT(devad) (1 << (devad)) -- 2.35.1.1320.gc452695387.dirty
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