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Subject[PATCH v2] PCI: Fix up L1SS capability for Intel Apollolake PCIe bridge
Date
On Google Coral and Reef family chromebooks, the PCIe bridge lost its
L1 PM Substates capability after resumed from D3cold, and identify that
the pointer to the this capability and capapability header are missing
from the capability list.

....
Capabilities: [150 v0] Null
Capabilities: [200 v1] L1 PM Substates
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ...
PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
T_CommonMode=40us LTR1.2_Threshold=98304ns
L1SubCtl2: T_PwrOn=60us
...

This patch fix up the header and the pointer to the L1SS capability
after resuming from D3Cold.

Signed-off-by: Ron Lee <ron.lee@intel.com>
Reported-by: kernel test robot <lkp@intel.com>
---
drivers/pci/quirks.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 285acc4aaccc..fc959be17a9d 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5992,3 +5992,20 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
#endif
+
+#ifdef CONFIG_PCIEASPM
+static void chromeos_fixup_apl_bridge_l1ss_capability(struct pci_dev *pdev)
+{
+ if (!dmi_match(DMI_SYS_VENDOR, "Google") ||
+ (!dmi_match(DMI_PRODUCT_FAMILY, "Google_Coral") &&
+ !dmi_match(DMI_PRODUCT_FAMILY, "Google_Reef")))
+ return;
+
+ pci_info(pdev, "Fix up L1SS Capability\n");
+ /* Fix up the L1SS Capability Header*/
+ pci_write_config_dword(pdev, pdev->l1ss, (0x220 << 20) | (1 << 16) | (PCI_EXT_CAP_ID_L1SS));
+ /* Fix up the pointer to L1SS Capability*/
+ pci_write_config_dword(pdev, 0x150, pdev->l1ss << 20);
+}
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_bridge_l1ss_capability);
+#endif
base-commit: e2ca6ba6ba0152361aa4fcbf6067db71b2c7a770
--
2.17.1

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