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SubjectRe: [PATCH] LoongArch: Correct the definition of is_branch_ins()
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Hi, Tiezhu,


On 2022-12-14 16:30, Tiezhu Yang wrote:
> The current definition of is_branch_ins() is not correct,

But the branch instruction opcode only use the high 6 bits, [1]. That's
meaningless because it is the same as the original result. If we care
too much about the details of instruction format, we will lose a lot of
tricks on LoongArch instruction coding.

[1]
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#table-of-instruction-encoding


> it was
> first introduced in commit 49aef111e2da ("LoongArch: Add prologue
> unwinder support"), in fact, there exist three branch instruction
> formats rather than only reg1i21_format.
>
> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/loongarch/include/asm/inst.h | 27 +++++++++++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/inst.h b/arch/loongarch/include/asm/inst.h
> index c00e151..42be39be 100644
> --- a/arch/loongarch/include/asm/inst.h
> +++ b/arch/loongarch/include/asm/inst.h
> @@ -329,8 +329,31 @@ static inline bool is_pc_ins(union loongarch_instruction *ip)
>
> static inline bool is_branch_ins(union loongarch_instruction *ip)
> {
> - return ip->reg1i21_format.opcode >= beqz_op &&
> - ip->reg1i21_format.opcode <= bgeu_op;
> + switch (ip->reg0i26_format.opcode) {
> + case b_op:
> + case bl_op:
> + return true;
> + }
> +
> + switch (ip->reg1i21_format.opcode) {
> + case beqz_op:
> + case bnez_op:
> + case bceqz_op:
> + return true;
> + }
> +
> + switch (ip->reg2i16_format.opcode) {
> + case jirl_op:
> + case beq_op:
> + case bne_op:
> + case blt_op:
> + case bge_op:
> + case bltu_op:
> + case bgeu_op:
> + return true;
> + }
> +
> + return false;
> }
>
> static inline bool is_ra_save_ins(union loongarch_instruction *ip)

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