lkml.org 
[lkml]   [2022]   [Dec]   [12]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
From
Subject[PATCH] pwm: xilinx: Fix overflow issue in 32-bit width PWM mode.
Date
This timer HW supports 8, 16 and 32-bit timer widths. This
driver uses a u32 to store the max value of the timer.
Because addition is done to this max value, when operating
in 32-bit mode, this will result in overflow that makes it
impossible to set the timer period and thus the PWM itself.

To fix this, simply make max a u64. This was tested on a
Zynq UltraScale+.

Signed-off-by: Ken Sloat <ksloat@designlinxhs.com>
---
include/clocksource/timer-xilinx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/clocksource/timer-xilinx.h b/include/clocksource/timer-xilinx.h
index c0f56fe6d22a..d116f18de899 100644
--- a/include/clocksource/timer-xilinx.h
+++ b/include/clocksource/timer-xilinx.h
@@ -41,7 +41,7 @@ struct regmap;
struct xilinx_timer_priv {
struct regmap *map;
struct clk *clk;
- u32 max;
+ u64 max;
};

/**
--
2.17.1




\
 
 \ /
  Last update: 2022-12-12 15:00    [W:0.102 / U:0.188 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site