Messages in this thread Patch in this message | | | From | Conor Dooley <> | Subject | [PATCH] Documentation: riscv: note that counter access is part of the uABI | Date | Thu, 1 Dec 2022 13:51:10 +0000 |
| |
Commit 5a5294fbe020 ("RISC-V: Re-enable counter access from userspace") fixed userspace access to CYCLE, TIME & INSTRET counters and left a nice comment in-place about why they must not be restricted. Since we now have a uABI doc in RISC-V land, add a section documenting it.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Based on an, as yet, unsent v2 of my other uABI changes. I don't expect it to be applicable, just getting a patch into patchwork while I don't forget about this. --- Documentation/riscv/uabi.rst | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/Documentation/riscv/uabi.rst b/Documentation/riscv/uabi.rst index 8d2651e42fda..638ddce56700 100644 --- a/Documentation/riscv/uabi.rst +++ b/Documentation/riscv/uabi.rst @@ -3,6 +3,13 @@ RISC-V Linux User ABI ===================== +Counter access +-------------- + +Access to the CYCLE, TIME and INSTRET counters, now controlled by the SBI PMU +extension, were part of the ISA when the uABI was frozen & so remain accessible +from userspace. + ISA string ordering in /proc/cpuinfo ------------------------------------ base-commit: 13ee7ef407cfcf63f4f047460ac5bb6ba5a3447d prerequisite-patch-id: d17a9ffb6fcf99eb683728da98cd50e18cd28fe8 prerequisite-patch-id: 0df4127e3f4a0c02a235fea00bcb69cd94fabb38 prerequisite-patch-id: 171724b870ba212b714ebbded480269accd83733 -- 2.38.1
| |