Messages in this thread Patch in this message | | | From | zhengjun.xing@linux ... | Subject | [PATCH v2 4/5] perf vendor events: Add the cpuid for Alderlake-N | Date | Mon, 21 Nov 2022 16:20:57 +0800 |
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From: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side, add the cpuid for Alderlake-N separately.
Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> --- Change log: v2: * Regenerate the mapfile with the new converter scripts. (https://github.com/intel/perfmon/pull/32 and add the ADL-N fix) * Change to the end of the ADL-N patch series * Only update the version for ADL-N
tools/perf/pmu-events/arch/x86/mapfile.csv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 5e609b876790..78af105ca236 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,5 +1,6 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-(97|9A|B7|BA|BE|BF),v1.15,alderlake,core +GenuineIntel-6-(97|9A|B7|BA|BF),v1.15,alderlake,core +GenuineIntel-6-BE,v1.16,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-56,v23,broadwellde,core -- 2.25.1
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