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    Subject[PATCH v2 7/8] riscv: dts: starfive: Add StarFive JH7110 VisionFive2 board device tree
    Date
    From: Emil Renner Berthing <kernel@esmil.dk>

    Add a minimal device tree for StarFive JH7110 VisionFive2 board.
    Support booting and basic clock/reset/pinctrl/uart drivers.

    Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
    Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
    Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
    Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
    Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
    ---
    arch/riscv/boot/dts/starfive/Makefile | 1 +
    .../jh7110-starfive-visionfive-v2.dts | 116 ++++++++++++++++++
    2 files changed, 117 insertions(+)
    create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts

    diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
    index 0ea1bc15ab30..e1237dbc6aac 100644
    --- a/arch/riscv/boot/dts/starfive/Makefile
    +++ b/arch/riscv/boot/dts/starfive/Makefile
    @@ -1,2 +1,3 @@
    # SPDX-License-Identifier: GPL-2.0
    dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
    +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb
    diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
    new file mode 100644
    index 000000000000..c8946cf3a268
    --- /dev/null
    +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
    @@ -0,0 +1,116 @@
    +// SPDX-License-Identifier: GPL-2.0 OR MIT
    +/*
    + * Copyright (C) 2022 StarFive Technology Co., Ltd.
    + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
    + */
    +
    +/dts-v1/;
    +#include "jh7110.dtsi"
    +#include <dt-bindings/gpio/gpio.h>
    +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
    +
    +/ {
    + model = "StarFive VisionFive V2";
    + compatible = "starfive,visionfive-v2", "starfive,jh7110";
    +
    + aliases {
    + serial0 = &uart0;
    + };
    +
    + chosen {
    + linux,initrd-start = <0x46100000>;
    + linux,initrd-end = <0x4c000000>;
    + stdout-path = "serial0:115200";
    + };
    +
    + cpus {
    + timebase-frequency = <4000000>;
    + };
    +
    + memory@40000000 {
    + device_type = "memory";
    + reg = <0x0 0x40000000 0x1 0x0>;
    + };
    +
    + gpio-restart {
    + compatible = "gpio-restart";
    + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
    + priority = <224>;
    + };
    +};
    +
    +&osc {
    + clock-frequency = <24000000>;
    +};
    +
    +&clk_rtc {
    + clock-frequency = <32768>;
    +};
    +
    +&gmac0_rmii_refin {
    + clock-frequency = <50000000>;
    +};
    +
    +&gmac0_rgmii_rxin {
    + clock-frequency = <125000000>;
    +};
    +
    +&gmac1_rmii_refin {
    + clock-frequency = <50000000>;
    +};
    +
    +&gmac1_rgmii_rxin {
    + clock-frequency = <125000000>;
    +};
    +
    +&i2stx_bclk_ext {
    + clock-frequency = <12288000>;
    +};
    +
    +&i2stx_lrck_ext {
    + clock-frequency = <192000>;
    +};
    +
    +&i2srx_bclk_ext {
    + clock-frequency = <12288000>;
    +};
    +
    +&i2srx_lrck_ext {
    + clock-frequency = <192000>;
    +};
    +
    +&tdm_ext {
    + clock-frequency = <49152000>;
    +};
    +
    +&mclk_ext {
    + clock-frequency = <12288000>;
    +};
    +
    +&gpio {
    + uart0_pins: uart0-0 {
    + tx-pins {
    + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;
    + bias-disable;
    + drive-strength = <12>;
    + input-disable;
    + input-schmitt-disable;
    + slew-rate = <0>;
    + };
    +
    + rx-pins {
    + pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
    + bias-pull-up;
    + drive-strength = <2>;
    + input-enable;
    + input-schmitt-enable;
    + slew-rate = <0>;
    + };
    + };
    +};
    +
    +&uart0 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&uart0_pins>;
    + status = "okay";
    +};
    --
    2.38.1
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