Messages in this thread Patch in this message | | | From | Prabhakar <> | Subject | [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically | Date | Fri, 28 Oct 2022 17:59:15 +0100 |
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- v4 -> v5 * Included RB tag from Conor
v3 -> v4 * Included RB tag from Heiko
v2 -> v3 * Included RB tag from Geert
v1 -> v2 * Included RB tag from Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 90a7cabf58fe..ae7963e99225 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,17 +28,17 @@ properties: oneOf: - items: - enum: - - sifive,rocket0 + - canaan,k210 - sifive,bullet0 - sifive,e5 - sifive,e7 - sifive,e71 - - sifive,u74-mc - - sifive,u54 - - sifive,u74 + - sifive,rocket0 - sifive,u5 + - sifive,u54 - sifive,u7 - - canaan,k210 + - sifive,u74 + - sifive,u74-mc - const: riscv - items: - enum: -- 2.25.1
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