Messages in this thread | | | Subject | Re: [PATCH 4/4] arm64: dts: uniphier: Add NX1 SoC and boards support | From | Kunihiko Hayashi <> | Date | Thu, 27 Oct 2022 20:19:34 +0900 |
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Hi Arnd,
Thank you for your comment.
On 2022/10/27 19:01, Arnd Bergmann wrote: > On Thu, Oct 27, 2022, at 06:51, Kunihiko Hayashi wrote: >> Initial version of devicetree sources for NX1 SoC and boards. >> >> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > > Can you add more information here? When new SoCs get added, I > usually provide more than this in my own pull requests sending > the patches to Linus, so please add some background here, such as: > > - is this a new SoC, or or something that has been around for a while > and only now gets upstreamed? > > - What is the target market for this SoC? Are there any products > one can buy with it? > > - What type of CPU cores does it use, or any other noteworthy > IP blocks that are relevant for its purpose?
This advice is good for me. I'll add some background for this SoC to the commit.
>> + usb_hsphy0: hs-phy@200 { >> + compatible = > "socionext,uniphier-nx1-usb3-hsphy"; >> + reg = <0x200 0x10>; > >> + usb_ssphy0: ss-phy@300 { >> + compatible = > "socionext,uniphier-nx1-usb3-ssphy"; >> + reg = <0x300 0x10>; > > I think these are usually just named 'phy@' instead of 'hs-phy@'
I see. Since it was adapted to other SoCs, I'll rename the node as well in another patch.
>> + ranges = >> + /* downstream I/O */ >> + <0x81000000 0 0x00000000 0x0ffe0000 0 > 0x00010000>, >> + /* non-prefetchable memory */ >> + <0x82000000 0 0x20000000 0x04200000 0 > 0x0bde0000>; > > 200MB of memory space is rather small, is there no 64-bit range?
Unfortunately, this SoC has only 190MB of PCIe memory space.
>> + #interrupt-cells = <1>; >> + interrupt-names = "dma", "msi"; >> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ >> + <0 0 0 2 &pcie_intc 1>, /* INTB */ >> + <0 0 0 3 &pcie_intc 2>, /* INTC */ >> + <0 0 0 4 &pcie_intc 3>; /* INTD */ >> + phy-names = "pcie-phy"; >> + phys = <&pcie_phy>; >> + >> + pcie_intc: legacy-interrupt-controller { >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + interrupt-parent = <&gic>; >> + interrupts = <GIC_SPI 86 > IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; > > Shouldn't there be an "msi-map" or "msi-parent" property pointing at > the GIC?
Since Designware PCIe receives an interrupt from GIC with interrupt-name "msi" and passes the interrupt to the linear irq domain corresponding to MSI, I think there is neither "msi-map" nor "msi-parent" properties.
Thank you,
--- Best Regards Kunihiko Hayashi
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