Messages in this thread | | | From | Chen-Yu Tsai <> | Date | Fri, 7 Jan 2022 14:19:40 +0800 | Subject | Re: [PATCH v7 4/4] arm64: dts: Add mediatek SoC mt8195 and evaluation board |
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On Thu, Dec 23, 2021 at 5:59 PM Chen-Yu Tsai <wenst@chromium.org> wrote: > On Mon, Dec 20, 2021 at 8:20 PM Tinghan Shen <tinghan.shen@mediatek.com> wrote:
> > + infracfg_rst: reset-controller { > > + compatible = "ti,syscon-reset"; > > + #reset-cells = <1>; > > + ti,reset-bits = < > > + 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) > > + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) > > + 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) > > + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) > > This should be 7 cells per entry: > > ti,reset-bits = > <0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE>, > <0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)>, > <...>, > <...>;
Please ignore this comment. It looks like I misread the binding, and your version is correct. However please format the columns so they align.
ChenYu
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