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SubjectRe: [PATCH] dt-bindings: nand: meson: fix controller clock
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Hi Miquel,

On 2022/1/6 16:12, Miquel Raynal wrote:
> [ EXTERNAL EMAIL ]
>
> Hello,
>
> liang.yang@amlogic.com wrote on Thu, 6 Jan 2022 11:31:30 +0800:
>
> This patch should be in a series with "mtd: rawnand: meson: fix the
> clock after discarding sd_emmc_c_clk" and possibly come first.
>
> You miss a commit message which is _very_ important given the type of
> change you propose.
>
>> Change-Id: I1425b491d8b95061e1ce358ef33143433fc94d24
>
> Change IDs have nothing to do here.
>
> However a Fixes and a Signed-off-by are welcome.
>
> You'll also need to Cc: Rob H. in your v2.
>
ok, i will fix these once we clarify the patch about sd_emmc_c_clk and
decide to use this patch.
>> ---
>> .../bindings/mtd/amlogic,meson-nand.txt | 18 +++---------------
>> 1 file changed, 3 insertions(+), 15 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> index 5794ab1147c1..37f16fe4fe66 100644
>> --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
>> @@ -14,11 +14,6 @@ Required properties:
>> - clock-names: Should contain the following:
>> "core" - NFC module gate clock
>> "device" - device clock from eMMC sub clock controller
>> - "rx" - rx clock phase
>> - "tx" - tx clock phase
>> -
>> -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC
>> - controller port C
>>
>> Optional children nodes:
>> Children nodes represent the available nand chips.
>> @@ -28,11 +23,6 @@ see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindi
>>
>> Example demonstrate on AXG SoC:
>>
>> - sd_emmc_c_clkc: mmc@7000 {
>> - compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
>> - reg = <0x0 0x7000 0x0 0x800>;
>> - };
>> -
>> nand-controller@7800 {
>> compatible = "amlogic,meson-axg-nfc";
>> reg = <0x0 0x7800 0x0 0x100>;
>> @@ -41,11 +31,9 @@ Example demonstrate on AXG SoC:
>> interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
>>
>> clocks = <&clkc CLKID_SD_EMMC_C>,
>> - <&sd_emmc_c_clkc CLKID_MMC_DIV>,
>> - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>,
>> - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>;
>> - clock-names = "core", "device", "rx", "tx";
>> - amlogic,mmc-syscon = <&sd_emmc_c_clkc>;
>> + <&clkc CLKID_FCLK_DIV2>;
>> + clock-names = "core", "device";
>> + sd_emmc_c_clkc = <0xffe07000>;
>>
>> pinctrl-names = "default";
>> pinctrl-0 = <&nand_pins>;
>
>
> Thanks,
> Miquèl
>
> .

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