| Subject | Re: [PATCH v3 12/33] iommu/mediatek: Always tlb_flush_all when each PM resume | From | AngeloGioacchino Del Regno <> | Date | Tue, 4 Jan 2022 16:55:39 +0100 |
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Il 23/09/21 13:58, Yong Wu ha scritto: > Prepare for 2 HWs that sharing pgtable in different power-domains. > > When there are 2 M4U HWs, it may has problem in the flush_range in which > we get the pm_status via the m4u dev, BUT that function don't reflect the > real power-domain status of the HW since there may be other HW also use > that power-domain. > > The function dma_alloc_attrs help allocate the iommu buffer which > need the corresponding power domain since tlb flush is needed when > preparing iova. BUT this function only is for allocating buffer, > we have no good reason to request the user always call pm_runtime_get > before calling dma_alloc_xxx. Therefore, we add a tlb_flush_all > in the pm_runtime_resume to make sure the tlb always is clean. > > Another solution is always call pm_runtime_get in the tlb_flush_range. > This will trigger pm runtime resume/backup so often when the iommu > power is not active at some time(means user don't call pm_runtime_get > before calling dma_alloc_xxx), This may cause the performance drop. > thus we don't use this. > > In other case, the iommu's power should always be active via device > link with smi. > > The previous SoC don't have PM except mt8192. the mt8192 IOMMU is display's > power-domain which nearly always is enabled. thus no need fix tags here. > Prepare for mt8195. > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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