Messages in this thread Patch in this message | | | From | Tony Luck <> | Subject | [PATCH v2 1/6] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN | Date | Fri, 21 Jan 2022 09:47:38 -0800 |
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Missed adding the Icelake-D CPU to the list. It uses the same MSRs to control and read the inventory number as all the other models.
Reported-by: Ailin Xu <ailin.xu@intel.com> Fixes: dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN") Cc: <stable@vger.kernel.org> Signed-off-by: Tony Luck <tony.luck@intel.com> --- arch/x86/kernel/cpu/mce/intel.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index bb9a46a804bf..baafbb37be67 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: case INTEL_FAM6_ICELAKE_X: + case INTEL_FAM6_ICELAKE_D: case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: -- 2.31.1
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