Messages in this thread | | | From | Tim Harvey <> | Date | Wed, 12 Jan 2022 10:24:29 -0800 | Subject | Re: [PATCH net-next v6] net: phy: intel-xway: Add RGMII internal delay configuration |
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On Wed, Jan 12, 2022 at 5:14 AM Andrew Lunn <andrew@lunn.ch> wrote: > > > > If I add a 'genphy_soft_reset(phydev);' at the top of > > > xway_gphy_rgmii_init before the write to XWAY_MDIO_MIICTRL the values > > > do take effect so perhaps that's the proper fix. > > > > OK, I see that we have to change something here. > > But I would like to avoid a complete reset (BMCR_RESET) if possible. > > What does the datasheet say about BMCR_RESET? Some PHYs, like Marvell, > it only resets the internal state machines. Register values are not > changed back to defaults or anything like that. Also for many register > writes in Marvell PHYs the write does not take effect until the next > reset. > > So a BMCR_RESET can be the correct thing to do. >
Andrew,
Datasheet [1] says "Resets the PHY to its default state. Active links are terminated. Note that this is a self-clearing bit which is set to zero by the hardware after reset has been done. See also IEEE 802.3-2008 22.2.4.1.1."
Experimentally I can change the delays and read them back as such, then issue a BMCR_RESET and read them and they revert to strapped values so I know BMCR_RESET resets at least some of the registers.
I suppose something to force auto-negotiation to occur again (BMCR_ANEN?) would suffice. I'm not sure what the best course of action is.
Tim [1] https://assets.maxlinear.com/web/documents/618152_gpy111_pef7071vv16_hd_rev1.5.pdf
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